The PCB Design Quiz: Seven Questions to Sharpen Your Skills

In high‑speed digital and power electronics, small design choices can have a major impact on signal integrity (SI), electromagnetic interference (EMI) performance, and overall system reliability. From understanding how signals propagate to optimizing capacitor placement, stackups, connector pinouts, and grounding strategies, each detail shapes the behavior of circuits in subtle but important ways.

In this article, we walk through seven practical questions to highlight common design pitfalls, explain why they matter, and show how thoughtful layout and grounding decisions lead to cleaner, more robust designs.

Question 1

Traveling through air, which conductor will deliver signals the fastest? Air-filled coax cable, superconductor wire, power lines, breadboard wires?

This is a bit of a trick question. What we call “signal speed” is actually the propagation speed of an electromagnetic wave, which depends entirely on the surrounding dielectric, not the conductor material. Conductors mainly serve to guide the wave, not set its speed.

Since all these signals are in air, the signals travel at the same speed in all cases.

Question 2

How does decoupling capacitor mounting affect its ability to lower the power network’s impedance? Can you explain which strategies shown below are best?

At its core, good capacitor placement comes down to one principle: minimizing impedance between the capacitor and the power/ground planes. In this context, impedance is dominated by inductance, so the real goal is reducing the inductance in the current loop formed between the capacitor pads and the planes.

To reduce that inductance, focus on the shape and size of the loop:

• Wider traces reduce inductance, so make these traces as wide as your layout allows.
• Smaller loops reduce inductance. The bigger the physical loop between the capacitor pads and the planes, the more inductance you introduce.

We apply these principles through a few practical layout choices:

• Place power and ground vias as close together as possible.
• Use multiple via pairs in parallel to further lower inductance (inductors in parallel).

When we evaluate the example layouts with these rules in mind:

• Example 1: Worse case, thin traces and widely spaced vias
• Example 2: Slight improvement, but still not great
• Examples 3 and 4: Good, short traces and tighter via spacing
• Example 5: Best, wide traces, close vias, and two via pairs in parallel

The takeaway: Short, wide connections and tightly paired vias dramatically improve capacitor performance by shrinking inductance. Small layout details add up to big gains in PDN quality.

Question 3

Which 8-layer stackup is better for a PCBA with many switching integrated circuits (ICs)?

When building stackups for high-speed digital (or ‘switching’) signals, two priorities dominate: power delivery and solid signal referencing.

For strong power delivery, you want the power and ground planes placed as close together as possible. A tight separation lowers the impedance of the power delivery network, improving stability and reducing noise. In stackup 2, the power and ground planes are spaced farther apart and separated by a signal layer, which increases PDN impedance and can degrade performance.

From a referencing perspective, both stackups provide workable options, but when you balance referencing with the need for low-impedance power delivery, stackup 1 is the better overall choice.

The bottom line: closely coupled power and ground planes are essential for robust digital design, which makes stackup 1 the more effective configuration.

Question 4

Look at this layout image. Can you spot the problems with how the signal traces on Layer 1 (green) are routed over the power/ground plane on Layer 2 (red)?

In this image, the green traces represent signals on Layer 1, and the red areas on Layer 2 are the power and ground planes. The issue here is return path discontinuities, often called broken return paths.

A digital signal’s return current naturally flows directly beneath its trace on the nearest reference plane. As long as that plane is continuous, the current loop stays tight and controlled. But what happens when a trace crosses a split in the plane?

The return current still finds a way, but not a good one. It spreads out across the board, following a much larger and uncontrolled path. This expanded field can lead to increased EMI, higher noise, and signal integrity problems.

The takeaway: avoid routing signals over breaks in the reference plane. Keeping return paths continuous ensured cleaner signals and a more predictable design.

Question 5

In the image below, which pinout will have fewer SI and EMI problems and why?

Connector pinouts are a frequent trouble spot for both SI and EMC. As signals leave a well-controlled impedance environment on the PCB and enter the connector, they often encounter a less organized layout that can create problems. Two key factors make the difference:

1. Sufficient return paths. More return pins help confine signal fields, reducing EMI. While a 1:1 signal-to-return ratio is ideal, it isn’t practical for many designs. As a rule of thumb, an absolute minimum of a 4:1 ratio (signals to returns) should be maintained to keep emissions in check.
2. Well-distributed return pins. When all returns are grouped at one end of the connector, signal fields must spread further to reach them. This wider spread increases the chances of those fields interacting with other signal traces, leading to crosstalk. Spacing return pins throughout the connector helps contain fields and improves performance.

With these principles in mind, it’s clear why a connector layout like Connect 2 performs better: it offers more return paths, and those returns are strategically spaced among the signal pins, reducing both EMI and crosstalk risk.

Question 6

In the image below, how do these stubs affect signals?

As a signal travels from its driver along a 50 Ω transmission line, any attached stubs create impedance changes that disrupt the signal. Each stub is also 50 Ω, so when the main line encounters two stubs in parallel, the signal effectively sees 25 Ω. Any change in impedance, like this drop from 50 Ω to 25 Ω, creates reflections.

Those reflections don’t just come from the stubs. They also occur at the receivers, which present a very high impedance. The combination of reflections from both stubs and receivers overlaps in time, adding unnecessary noise into the system.

However, when stubs are kept very short, the situation improves dramatically. A short stub looks like a 50 Ω path in parallel with a very high-impedance path. That combination is still near 50 Ω, so the reflections caused by the stub become much smaller. Less reflection means less noise and cleaner signaling.

The bottom line: eliminate stubs whenever possible. If stubs are required, keep them as short as you can. As the results show, even small reductions in stub length can make a significant impact on signal quality.

Question 7

In the image below, which grounding configuration will have fewer SI/EMI problems?

The two enclosed systems are connected using a shielded cable that’s bonded 360° to the chassis at both ends. The harness carries multiple digital signals and one low-frequency analog signal, and each system ties its PCB ground to its chassis.

The challenge arises with that low-frequency signal. Low-frequency currents follow the path of least resistance. When the signal reaches the second system, it can return either through the designated return wires in the harness or through the low-resistance chassis connection. That alternative chassis path creates a ground loop, one that can lead to EMI issues.

Using a capacitive bond at the chassis changes his behavior. A capacitor blocks low-frequency currents, forcing the analog signal to return through the harness instead of through the chassis. In other words, the design ‘steers’ the low-frequency current back along the intended path.

You might wonder why the return paths don’t matter as much for the digital signals. Digital signals are high‑frequency, and high‑frequency currents follow the path of least inductance, not least resistance. The inductance of a chassis loop is far greater than the inductance of the harness’s return conductors. That means digital signals naturally choose the proper harness returns. If the harness carried only digital signals, both grounding configurations would work fine.

There’s one more important factor: external noise coupling. In the solid-bond configuration, the shield and chassis form a conductive loop that external noise can easily couple into. Using a capacitor blocks low‑frequency noise from entering this loop. If you do choose the solid-bond approach, it’s wise to route the harness as close to the chassis as possible to minimize the loop area.

Elevate Your PCB Designs with EMA

Across all these questions, a consistent theme emerges: strong signal integrity and low EMI aren’t the result of any single trick, they come from understanding how electromagnetic fields behave and designing with those fundamentals in mind. Whether it’s choosing the right stackup, tightening a capacitor’s current loop, preserving reference planes, or managing return paths through connectors and grounding schemes, the details matter. By applying these principles early and intentionally, designers can avoid common pitfalls, improve robustness, and build systems that perform reliably in real‑world environments.

Electro Magnetic Applications, Inc. (EMA) offers PCB design review services to help teams catch issues early, strengthen designs, and avoid costly rework down the line. Our engineers have practical experience in signal integrity, power delivery, EMC, and layout best practices, providing the clarity and confidence needed to move from concept to production.

If you’d like expert support evaluating your board or solving challenging design problems, reach out to EMA. We’re here to help you build smarter, cleaner, and more reliable products.